A construction of a prior art resettable frequency divider circuit will be described.
FIG. 11 shows a construction of a prior art 1/16 frequency divider circuit. In FIG. 11, reference numerals 11B to 14B designate 1/2 frequency divider circuits, respectively, which are triggered type flip-flops having reset functions. Reference numeral 32 designates a buffer circuit for receiving a reset signal. Reference characters IN and OUT designate a signal input terminal and a signal output terminal of the resettable frequency divider circuit, respectively. Reference characters N1 to N3 designate output terminals of the 1/2 frequency divider circuits 11B to 13B, respectively. Reference character N4 designates an output terminal of the buffer circuit 32 for the reset signal. Reference character RS designates a reset signal input terminal. Reference characters D, Q, and R designate input terminals, output terminals, and reset signal input terminals of the 1/2 frequency divider circuits 11B to 14B, respectively.
This frequency divider circuit will operate as follows.
When a reset signal is input to the respective 1/2 frequency divider circuits 11B to 14B, the internal signals thereof are compulsorily set to "High" or "Low" state. When the reset signal is cancelled, the respective 1/2 frequency divider circuits divide the input frequency, and the entire circuit conducts a 1/16 frequency division operation.
This operation will be described in detail with reference to FIGS. 12A and 12B.
FIGS. 12A and 12B show a relationship between an output signal and a reset input signal of the resettable frequency divider circuit. Herein, the respective 1/2 frequency divider circuits are triggered type flip-flops which change their output signals when the input signals are changed to "High", and the internal nodes of the flip-flops are set to "Low" by the reset signal. In FIG. 12A, reference character OUT designates an output signal of the resettable frequency divider circuit. Reference character RS in FIG. 12B designates a reset input signal. Reference character T in FIG. 12A designates the period of the output signal of the frequency divider circuit. When a reset signal is input, all internal nodes of the frequency divider circuit are set to "Low" and the output signal (OUT) is set to a state immediately before "High" state. The output signal (OUT) of the frequency divider circuit becomes "High" when the reset signal is cancelled, and a frequency division is again started. Thus, the time period from the cancellation of the reset signal to the rise of the next output is a period T, and this frequency divider circuit is set to an initial state by the reset signal.
FIG. 14 shows another prior art frequency divider circuit having a division ratio of 1/256 and 1/257. In FIG. 14, reference numeral 33 designates a two-mode frequency divider circuit comprising D flip-flops 33a, 33b, and 33c, which conducts 1/4 and 1/5 frequency division, alternatively. Reference numerals 11B to 16B designate 1/2 frequency divider circuits, respectively, which are T flip-flops. Reference numerals 30, 31, 34, and 35 designate OR circuits. Reference character IN designates a signal input terminal. Reference character MOD designates an input terminal for receiving a frequency division switching signal. Reference character OUT designates an output terminal. Reference character RS designates a reset signal input terminal.
The operation of this frequency divider circuit at the resetting is as follows. When the RS signal is "High", reset signals are input to the respective D flip-flops 33a to 33c and T flip-flops 11B to 16B, and the operation of the entire circuit is halted.
In these prior art frequency divider circuits, in order to conduct a reset operation, all flip-flops are required to have reset functions.
FIG. 13 shows a construction of a 1/2 frequency divider circuit having a reset function including field effect transistors. In FIG. 13, reference characters J1 to J13, J21, and J22 designate transistors. Reference characters R1 to R4 designate resistors. Reference characters I1 to I3 designate constant current sources. Reference character V.sub.DD designates a power supply terminal. Reference character D.sub.IN designates an input signal terminal. Reference character D.sub.R designates a reference voltage signal input terminal. Reference character RS designates a reset signal input terminal. Reference character OUT designates an output terminal. In this 1/2 frequency divider circuit, transistors J21 and J22 ar newly provided as compared with a usual 1/2 frequency divider circuit having no reset function.
The operation of this 1/2 frequency divider circuit will be briefly described.
When the reset input signal RS is "Low", the transistors J21 and J22 are in OFF states, and the frequency divider circuit operates as it the transistors J21 and J22 were not present, that is, it conducts a 1/2 frequency division operation. When the reset input signal RS is "High", the transistors J21 and J22 are in ON state and the currents flowing through the resistors R2 and R4 become larger than the currents flowing through the resistors R1 and R3, and the 1/2 frequency divider circuit is set to "Low" state.
In the prior art resettable frequency divider circuit, transistors for providing a reset function have to be provided inside the respective 1/2 frequency divider circuits, and this results in a reduction in the operation speed or an increase in the number of elements to provide a reset function. Furthermore, since the reset signals have to be given to all 1/2 frequency divider circuits, a buffer circuit is required for supplying reset signals to all flip-flops, and this results in an increase in power dissipation.